Electrostatic discharge (ESD), which is a large subset of electrical overstress (EOS), is a major reliability issue in integrated circuits (ICs). EOS and ESD together account for more than 60% of failures in ICs. As semiconductor devices have scaled to smaller dimensions and ICs have become more complex, the potential for destructive ESD events has become more serious.
More recently, there has been a tremendous demand for increasing the ESD robustness of Radio Frequency Integrated Circuits (RFICs) especially for wireless applications, since such products, typically handheld devices, are much more prone to ESD-induced damages.
FIG. 1 illustrates a conventional ESD protection circuit. As can be seen from FIG. 1, a voltage rail (Vcc) 10 and a ground rail (GND) 12 are illustrated. A protected circuit 14 is illustrated connected between the voltage rail 10 and the ground rail 12. A signal pin 20 provides a signal path to the protected circuit 14.
A conventional ESD protection circuit 22 is connected between the voltage rail 10 and the ground rail 12. The conventional ESD protection circuit 22 includes a diode 24 and a diode 26, which are connected in series. The cathode of diode 24 is connected to the voltage rail 10 and the anode is connected to the signal pin 20 at a node 30 on the signal path between the signal pin 20 and the protected circuit 14. The anode of the diode 26 is connected to the ground rail 12 and the cathode is connected to node 30 on the signal path from the signal pin 20 to the protected circuit 14.
For positive-going ESD surges on the signal pin 20, the diode 24 will become forward biased and will clamp the voltage on the signal pin 20 to one diode drop above the voltage rail 10. Energy from the ESD surge will be conducted through the diode 24 in a forward biased mode and dispersed into the voltage rail 10. Appropriate ESD protection structures have to be implemented (not shown) in the voltage rail 10 to eventually dissipate the ESD pulse to the ground rail 12.
For negative-going ESD surges on the signal pin 20, voltage on the signal pin 20 will be clamped to one diode drop below the ground rail 12 by the diode 26. Though the diode 26 will be in a forward biased mode, the diode 26 provides a low-impedance path relative to the protected circuit 14. Accordingly, energy from the ESD surge will be dissipated into the ground rail 12.
The conventional ESD protection circuit 22 of FIG. 1 is widely used in CMOS technologies. Accordingly, ESD protection for CMOS ICs is relatively mature. However, ESD protection circuitry for newer technologies is still in its infancy.
Gallium-Arsenide (GaAs) is often used for power amplifiers (PAs) and switches because of its intrinsically higher low-field electron mobility, transition frequency, and breakdown voltage. For low noise amplifiers, switches, and PAs, GaAs pseudomorphic high electron mobility transistor (pHEMT) technology is used. However, ESD protection circuitry for GaAs pHEMT technology that is currently in use provides undesirable characteristics.
Ideally, an ESD protection system must not affect the input/output (I/O) signal under normal operating conditions. However, current GaAs pHEMT ESD protection structures have unwanted parasitic capacitances and resistances which may adversely affect performance of radio frequencies (RF) circuits. In particular, at RF frequencies, the parasitics associated with the ESD structures can lead to impedance mismatches. Impedance mismatches can cause signal reflection which degrades the performance of the circuit which it is intended to be protected.
Additionally, a protection circuit, such as that shown in FIG. 1, is unsuitable for pHEMT switches. A signal presented to a pHEMT switch may swing to several times the supply voltage in the transmit port. Accordingly, a rail clamp, such as the diode 24 in FIG. 1, would “clip” the signal since the diode 24 is forward biased to the power rail when the signal swings to more than one diode drop above the voltage rail 10.
In an attempt to provide an ESD protection circuit which does not clamp the signal at one diode drop above a voltage rail, other ESD protection circuits used in pHEMT technology use a diode stack with diodes placed in a forward biased arrangement between the signal, such as node 30 of FIG. 1, and the ground rail 12. However, a diode stack for this application can result in a diode stack of nine or more diodes in such an application. For example, a pHEMT switch connected to a GSM power amplifier that can have an output power of 34 dBm may have an instantaneous voltage of more than three (3) times the power supply. Accordingly, for a six-volt power rail, an ESD protection circuit should remain inactive for voltages lower than eighteen (18) volts. Considering that the forward voltage drop of a diode in a diode stack will range from 0.6 to 0.7 volts, it is readily seen that a very large stack of diodes may be required in order to provide appropriate protection for the circuit.
The use of large diode stacks for ESD protection circuitry also increases diode size. Because each diode in a diode-stack configuration is connected in series, each diode in a stack must carry all of the current during an ESD event. Accordingly, all diodes in a diode stack must be dimensionally sized for carrying large ESD currents. This increase in diode size correlates to an increase in cost of manufacturing and, thereby, cost to consumers.
Another issue with the use of diode stacks is associated with the on-state resistance of the stack. Each diode in the stack has an on-state resistance associated with it. Accordingly, as the number of diodes in the stack increases, the on-state resistance of the stack also increases. This increase in resistance can increase the clamping voltage of the circuit to a level sufficient to damage the core circuitry that is to be protected.
A solution to the on-state resistance is to place several diode stacks in parallel. However, though paralleling several diode stacks improves the on-state resistance of the ESD protection circuit, it has two additional problems associated with it. First, by paralleling redundant stacks of diodes, the area required for the ESD protection circuitry increases dramatically. Second, because each diode has a parasitic capacitance associated with it as well, the parasitic capacitance of the ESD protection circuit increases as the number of diode stacks that are paralleled increases. This increase in parasitic capacitance negatively affects circuit performance, as described above.
Accordingly, an ESD protection circuit having a high trigger voltage that is small in size and has low on-state resistance and low parasitic capacitance is needed.